1. Field of the Invention
The present invention relates generally to current generating devices which respond to one-bit data to complementarily generate two currents of different magnitudes and, more particularly, to a reduction in switching time of the current generating devices and to a suppression in variations of generated currents.
2. Description of the Background Art
A D/A converter is employed for image data processing, a signal generation for controlling a mechanical apparatus, etc. Such a D/A converter is required to further enhance processing speed and the quality of signals.
In order to meet such requirements, a device is provided which responds to video data of a plurality of bits to generate two analog signals and apply one of the analog signals to a dummy load and the other signal to a load (CRT or the like) via a resistor for matching. This device is disclosed in, for example, the article entitled "A CMOS Triple 100 Mbit/s Video D/A Converter with Shift Register and Color Map", IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 21, No. 6, December 1986.
FIG. 7 is a schematic block diagram of a video data D/A converter described in this document. Referring to FIG. 7, this video data D/A converter includes a timing generation circuit 54 responsive to an externally applied pixel clock signal for generating a shift clock signal for internal synchronization, a shift register 51 for converting externally applied parallel video data into serial data, a color map memory 52 for storing color data or the like in advance, a D/A conversion circuit 53 for converting video data of a plurality of bits (16 bits) into complementary analog signals, and a processor interface 55 for writing color data or the like into color map memory 52 in advance and writing a program for serial/parallel conversion into shift register 51.
The video data D/A converter, performs the following operation. Video data of 16 bits is applied to shift register 51 and then converted into serial data of 4-6 bits therein. The converted data is then applied to color map memory 52. Color map memory 52 receives the video data from shift register 51 as address data and responds to a shift clock signal from timing generation circuit 54 to read previously written color data. The read color data is applied to D/A conversion circuit 53 and then converted into complementary analog signals by D/A conversion circuit 53. These analog signals are three types (red, blue, and green) and a synchronizing signal.
FIG. 8 is a circuit diagram showing the details of D/A conversion circuit 53. This D/A conversion circuit 53 includes a supply potential V.sub.DD, a ground potential GND, output terminals 01 and 02, current sources A1-A16, a dummy resistor R1 connected to output terminal 01, a resistor R2 for output matching connected between output terminal 02 and ground potential GND. Each of current sources A1-A16 includes PMOS transistors 1a, 1b, 2 and 3. PMOS transistors 1a and 1b are connected in series between supply potential V.sub.DD and a source (node N1) of PMOS transistor 2. A gate of PMOS transistor 1a is supplied with a bias signal V1a, and a gate of PMOS transistor 1b is supplied with a bias signal V1b. Respective drains of PMOS transistors 2 and 3 are connected to respective output terminals 01 and 02. Respective gates of PMOS transistors 2 and 3 are connected to corresponding ones of data input terminals -D1 to -D16 and +D1 to +D16, through which digital data are complementarily applied. Each of current sources A1-A16 responds to corresponding one-bit data of 16-bit complementary digital data to complementarily switch and generate two currents differing in magnitude. One of the generated two currents is supplied to output terminal 01, and the other is supplied to output terminal 02. As a result, output terminal 01 is provided with an analog signal which is a sum of respective currents flowing through respective PMOS transistors 2. Output terminal 02 is provided with an analog signal which is a sum of respective currents flowing through respective PMOS transistors 3. The analog signals thus obtained are complementary with each other.
As has been described above, complementary or differential switching of PMOS transistors 2 and 3 causes approximately constant currents to always flow through nodes N1. Thus, level changes of analog signals can be suppressed as compared with a switching made by a single switching element. The switching made by the single switching element requires the time to charge or discharge parasitic capacitances shown by the broken lines in FIG. 8. However, since constant currents always flow through nodes N1 by the differential operation of two switching elements, the time required for charging/discharging is unnecessary. This enables a shortening of switching time.
FIG. 9 is a circuit diagram showing an improvement of the current source of FIG. 8. This current source is of the one-bit scheme in order to simplify a description thereof. Referring to FIG. 9, this current source differs from the current source of FIG. 8 in that this current source is provided with a buffer circuit 60 which responds to one bit applied to data input terminals -D and +D to limit voltages to be applied to the respective gates of PMOS transistors 2 and 3. Limiting the gate voltages to be applied to PMOS transistors 2 and 3 suppresses the switching rate of PMOS transistors 2 and 3 and variations of analog signals.
PMOS transistors 2 and 3 to be controlled are, however, put in either a complete ON state or a complete OFF state. That is, resistances between drains and sources are put into either a lowest state or a highest state. It is thus possible that the variations of analog signals cannot sufficiently be suppressed, or the switching time cannot sufficiently be shortened.
FIG. 10 is a circuit diagram showing another example of a conventional current source. Referring to FIG. 10, this current source differs from the one shown in FIG. 9 in that this current source employs NMOS transistors 1, 2 and 3 in place of PMOS transistors 1a, 1b, 2 and 3 and employs a control signal generating circuit B and a supply circuit C in place of buffer circuit 60.
Control signal generating circuit B generates a first control signal V1 for operating NMOS transistor 1 in a saturation region and a second control signal V2 for operating NMOS transistors 2 and 3 in the saturation region. Generated first control signal V1 is output from a first control signal output terminal 4, and second control signal V2 is output from a second control signal output terminal 11.
Supply circuit C includes switch circuits SW1-SW4 which are rendered active when the one-bit data applied to data input terminals -D and +D is at a logic "1" level. Switch circuit SW1 switches between a gate 7 of NMOS transistor 2 and second control signal output terminal 11. Switch circuit SW2 switches between NMOS transistor 2 and a ground potential 5. Switch circuit SW3 switches between a gate 9 of NMOS transistor 3 and second control signal output terminal 11. Switch circuit SW4 switches between gate 9 of NMOS transistor 3 and ground potential 5.
A drain of NMOS transistor 2 is connected to an output terminal 01 which is connected with a supply potential V.sub.DD via a dummy resistor R1. A drain of NMOS transistor 3 is connected to an output terminal 02 which is connected with a load via an output matching resistor R2. Respective sources of NMOS transistors 2 and 3 are commonly connected to a drain (node 6) of NMOS transistor 1. A source of NMOS transistor 1 is connected to ground potential 5 and switch circuits SW2 and SW4. A gate of NMOS transistor 1 is supplied with the first control signal.
A description will now be given on an operation of the current source shown in FIG. 10. NMOS transistor 1 operates in a saturation region in response to the first control signal applied from first control signal output terminal 4, to generate a current with a constant magnitude. In this state, when data to be applied to data input terminal -D is "1" and data to be applied to data input terminal +D is "0", switch circuit SW1 is turned on and switch circuit SW2 is turned off. The turning on of switch SW1 causes second control signal V2 to be applied to gate 7 of NMOS transistor 2. As a result, a voltage on gate 7 rises depending on a time constant. The time constant is determined with ON-resistance of switch circuit SW1 and the capacitance between the gate and the source of NMOS transistor 2. When the voltage on gate 7 attains a predetermined potential, NMOS transistor 2 operates in the saturation region, so that a current flows through the path from output terminal 01 through NMOS transistors 2 and 1 to ground potential 5. At this time, since switch circuit SW3 is OFF and switch circuit SW4 is ON, a gate voltage of NMOS transistor 3 attains the ground potential, so that NMOS transistor 3 is turned off.
Conversely, when the data to be applied to data input terminals -D and +D are "0" and "1", respectively, switch circuits SW1 and SW4 are turned off and switch circuits SW2 and SW3 are turned on. As a result, gate 7 of NMOS transistor 2 is grounded, so that NMOS transistor 2 is turned off. Gate 9 of NMOS transistor 3 is supplied with second control signal V2 through second control signal output terminal 11. Accordingly, NMOS transistor 3 operates in the saturation region, so that a current flows from output terminal 02 through NMOS transistors 3 and 1 to ground potential 5. Thus, theoretically, a constant current always flows through NMOS transistor 1, and a potential on node 6 becomes constant.
In the above-described manner, with one of NMOS transistors 2 and 3 brought into a saturated state and the other transistor into OFF state, the current with a constant magnitude is provided at output terminal 01 or 02.
However, gate 7 of NMOS transistor 2 and gate 9 of NMOS transistor 3 are supplied with second control signal V2 and the ground potential via switch circuits SW1-SW4. Second control signal V2 is at a level for operating the NMOS transistors in the saturation region, and the ground potential is at a level for completely turning off the NMOS transistors. Thus, gate voltages having large amplitudes are applied to NMOS transistors 2 and 3.
FIGS. 11A and 11B are diagrams showing voltage changes and current changes in each circuit in the current source of FIG. 10. FIG. 11A shows a voltage 71 on gate 7 and a voltage 91 on gate 9; and FIG. 11B shows a potential 61 on common connection node 6 and a current 81 on output terminal 01. Referring to FIGS. 11A and 11B, if a second control signal is applied to gate 7 of NMOS transistor 2, so that gate 9 of NMOS transistor 3 attains a ground potential, then a deviation occurs in potential change of gate voltage 91 and gate voltage 71 due to influences by the ON-resistance of switch circuit SW1 and the parasitic capacitances on gate terminals of NMOS transistors 2 and 3. This causes a great fluctuation of voltage 61 on common connection node 6, which should ideally be constant, resulting in a great overshoot of output current 81 at output terminal 01.